Tech Sessions Abstracts

Technical Sessions 2026 - Abstracts

Keynote Address (Room 2, 8:30am - 9:15am)

· Speaker: Tyler Seeholzer – BETA Technologies - ALIA Training Program Manager

Session 3A (Room 3, 9:30am - 10:30am)

· Speaker: Michel Alexander – Cadence - Application Engineering Architect

· Title: Designing Electronics for What Comes Next

· Abstract: This presentation explores practical best practices for designing modern electronic systems, from PCB and package architecture to manufacturability, data management, and design reuse. Attendees will learn how disciplined libraries and constraints, a single source of truth, and shift-left simulation techniques can improve design quality while accelerating development cycles. The session will also discuss industry trends shaping the future of PCB design and the skills engineers need to remain effective in an increasingly connected, analysis-driven design environment.

Session 4A (Room 4, 9:30am - 10:30am)

· Speaker: Anton Nilsen – Fair-Rite Products – Field Application Engineer

· Title: Understanding EMI: Identifying Sources and Implementing Mitigation

· Abstract: Managing Electromagnetic Interference is a critical step for any reliable product design. This seminar provides an understanding of the primary sources of electromagnetic interference, the effect, and ferrite solutions to mitigate them. First, we'll take a high-level look at common sources of EMI and the type of protection provided to electronics from different means of suppression. We will finish off by seeing how ferrite can be implemented to mitigate this noise AND when it can't.

Session 5A (Room 5, 9:30am - 10:30am)

· Speaker: Matthias Zapatka – INGUN USA – Senior Field Application Engineer

· Title: Probe On Fire! Contact Force, Resistance, Temperature and its Impact on High

Current Measurements

· Abstract: In a production-line, spring-probes and contacts are a proven method to establish temporary but reliable electrical connection to a device-under-test; whether it’s a printed circuit board assembly (PCBA), a battery cell, or a whole high-power module.

With increased demands for power handling and current throughput, some testing solutions reach its limits as a spring-connection often does not have the same secure connection that a threaded connection would offer (= for permanent installation).

This presentation dives deep into topics such as how much contact force is needed to safely conduct higher currents for a given target, how to cool down the tip and body of a test probe and what contact resistance is and how it impacts those measurements. Why does sometimes every milliOhm count? What is an A-spot and how to maximize contact area? All those topics are shown in this year’s contribution for PCB Carolina.

The worst that can happen? A fire in the factory due to improper probe or fixturing choice. This sounds very dramatic but the purpose of this talk is not to get people away from using such parts, on the contrary the idea is to give insight how to correctly use spring-components that facilitate fast throughput of DUT’s – but without compromising safety.

We believe that these topics all deserve special consideration, as there are applications out there that truly go beyond “standard” conducted PCBA test (ICT/FCT). This is not only driven by the EV market or power-hungry AI applications – but also Mil/Aero boards and modules now require higher power and more current thruput than ever before. Join us this year for a captivating presentation and go back home with the assurance that your test probe choice won’t get the fire department or safety inspector involved.

While due diligence for proper probe choice is still necessary, we can arm you with the knowledge you need to make well-educated choices (= which force, tip, overall geometry and material to choose for a given application).

Session 6A (Room 6, 9:30am - 10:30am)

· Speaker: Gerry Callahan – U.S. Cargo Systems - Senior Electrical Engineer

· Title: Layout for Mixed Analog and Digital Boards

· Abstract: Layout of analog circuits is hard enough; same with digital. When you combine them on one board, you have all the same challenges plus some new ones. In this course, we will discuss those challenges and some solutions. Specifically, we’ll see how to maintain signal integrity in both domains, how to avoid EMC failures, and how to design a PCB stack-up

Session 3B (Room 3, 11:00am - 12:00pm)

· Speaker: Michael Catrambone – Cadence - Product Engineering Architect

· Title: The Future of PCB Design: Allegro X Platform Innovations for 2026

· Abstract: The Allegro X platform continues to advance, introducing new capabilities that help engineers design PCBs faster, smarter, and with greater connectivity.

This session will highlight the latest workflows and innovations shaping a more integrated platform experience—from a streamlined design cockpit to enhanced collaboration and increased productivity. Whether you are familiar with Allegro X or just beginning to explore it, you will see how modern, connected workflows can help you manage growing design complexity and stay ahead of what comes next.

Session 4B (Room 4, 11:00am - 12:00pm)

· Speaker: Dr. Bruce Archambeault -EMC Consultant / IEEE Fellow, Missouri S&T Adjunct Professor

· Title: Using State of the Art Software Tools to Help Insure Effective EMC

· Abstract: The demand for compact, high-performance electronics makes Ultra-High-Density Interconnect (UHDI) technologies crucial. This presentation explores UHDI topologies, enabling significantly higher wiring densities in electronic circuits. We'll cover essential design considerations like signal integrity, thermal management, and material selection, emphasizing early collaboration with PCB fabricators.

Discover how industry best practices integrate advanced materials, high-speed interconnects, and multi-layer architectures for optimized performance. We'll also examine the vital role of EDA tools for layout optimization, signal integrity simulation, and rigorous design rule checks. Verification techniques, including simulation, electrical/thermal analysis, and physical prototyping, will be discussed to ensure UHDI reliability and compliance.

Finally, we'll highlight emerging trends like AI/ML-driven design and innovative manufacturing, positioning UHDI as fundamental for industries from consumer electronics to aerospace. This session provides a comprehensive understanding of the evolving UHDI landscape, equipping you with insights for efficient design and robust verification of next-generation UHDI topologies.

What You Will Learn:

1. A practical understanding of UHDI PCB design principles.

2. Key design considerations: signal integrity, thermal management, material selection, and fabricator collaboration.

3. Insights into emerging UHDI trends, including AI/ML integration and miniaturization's impact.

Who Should Attend: PCB Designers, Design Engineers, System Architects.

Target Audience: Beginner, Intermediate, Advanced

Session 5B (Room 5, 11:00am - 12:00pm)

· Speaker: Dr. Steve Crane – ARA-I – Director, Labs Services

· Title: Lithium-Ion Battery Fires: From Factory Floor to Fire Scene

· Abstract: Lithium-ion battery fires are among the fastest-rising ignition sources in residential and commercial settings, driven by rapid product proliferation and systemic quality failures across the supply chain. This presentation delivers a rigorous engineering framework for understanding, investigating, and evaluating these events.

Beginning with the electrochemistry of thermal runaway, the self-sustaining exothermic cascade triggered by separator breach, dendrite formation, electrode contamination, or electrolyte decomposition, the session examines the full product ecosystem through which fire risk propagates - cells, packs, Battery Management Systems (BMS), chargers, and operation. Significant attention is given to manufacturing and supply-chain quality deficiencies as primary fire risk drivers: coating and dimensional defects, metallic particle contamination, counterfeit cell procurement, BMS protection inadequacies, and the safety-margin consequences of cost-reduction decisions. A number of applicable standards are referenced to inform both design compliance and expert opinions. Specific case studies are highlighted to connect such deficiencies in design & manufacturing to real-world loss scenarios.

Session 6B (Room 6, 11:00am - 12:00pm)

· Speaker: Stephen Chavez – Siemens – Principal Technical Product Marketing Manager

· Title: Mastering Ultra-High-Density Interconnect (UHDI) PCB Design for Next-Generation Electronics

What You Will Learn:

1. A practical understanding of UHDI PCB design principles.

2. Key design considerations: signal integrity, thermal management, material selection, and fabricator collaboration.

3. Insights into emerging UHDI trends, including AI/ML integration and miniaturization's impact.

Who Should Attend: PCB Designers, Design Engineers, System Architects.

Target Audience: Beginner, Intermediate, Advanced

Session 3C (Room 3, 2:00pm - 3:00pm)

· Speaker: Michael Catrambone – Cadence – Product Engineering Architect

· Title: Streamlining ECAD-MCAD Co-Design with IDX Data Exchange

· Abstract: Effective ECAD-MCAD collaboration is essential to accelerate product development, reduce design iterations, and avoid costly late-stage fit issues. Modern mechatronics demand a dynamic, tightly integrated workflow that goes beyond static, error-prone file formats such as STEP or DXF.

This presentation explores Incremental Design Exchange (IDX), an open standard for intelligent, bi-directional communication between ECAD and MCAD tools. Attendees will learn how IDX supports incremental design updates, visual change comparison, and structured approval workflows. The presentation will also cover best practices for building an efficient ECAD-MCAD co-design process, aligning components and board footprints, and using IDX to reduce revisions and shorten time-to-market.

Session 4C (Room 4, 2:00pm - 3:00pm)

· Speaker: Stephen Scearce – Amphenol – Senior Director, Cable Backplane Systems

· Title: High-Speed Cable Backplane Systems for AI Infrastructure: Engineering Challenges at 224G and 448G

· Abstract: As AI training and inference clusters scale to unprecedented bandwidth requirements, cable backplane interconnects have become a critical bottleneck and enabler for next-generation system architecture. This presentation examines the engineering challenges of designing, qualifying, and deploying high-speed cable backplane systems at 224 Gb/s and emerging 448 Gb/s data rates for AI infrastructure. Topics include signal integrity considerations for copper twinax cable at extreme data rates (including PAM4/PAM6 modulation schemes), mechanical float and connector design for reliable high-density interconnects, BERT-based qualification methodologies, and lessons learned from large-scale cartridge reliability programs. The talk will address the tradeoffs between insertion loss, reach, and manufacturability that engineering teams must navigate as the industry pushes toward higher bandwidth per lane and will share practical approaches to qualification and reliability testing that support high-volume deployment in AI data center environments.

Session 5C (Room 5, 2:00pm - 3:00pm)

· Speaker: Mohmed Abdelaal – Eurofins – Product Safety Engineer

· Title: Hazardous Location Certification and Compliance Services

· Abstract: The presentation is about the basic science and fundamentals of hazardous locations safety and certification, particularly in the USA, Canada, EU, and International (IECEx participating countries). The intended audience is industrial engineers, manufacturers, engineering students, and anyone who is interested in learning about what hazardous locations are. Main points:

* What are Hazardous Locations?

* How are they defined & classified around the world?

* How protection is achieved - protection methods

* Standards and Marking Strings

* Types of Hazloc certifications

Session 6C (Room 6, 2:00pm - 3:00pm)

· Speaker: Paul Cooke – Summit Interconnect - Director of Engineering

· Title: Advanced Processes to Meet Today’s Design Challenges

· Abstract: Designing printed circuit boards (PCB) and assemblies is more difficult than ever due to complexity, component availability, thermal requirements, signal integrity, material selection, layer counts, harsh environments and increased functionality all required in smaller form factors. We will look at all the elements to successfully manufacture a PCB that can meet all the designers’ requirements and perform to the customer and industry standards as well as survive in today’s harsh environment. We will look at some of the more advanced processes and materials being adopted by the fabricators to produce smaller, thinner, more reliable and faster production times to meet quick turn requirements. We will look at various processes and materials including plating shut, interposer designs, high reliability, high layer 5+ stacked microvia designs with 3 mil microvias, heavy copper solutions, and new hole fill processes without the need to planarize. All these processes need to ensure the product is robust as possible with a high level of confidence that it has been designed for extended life in the field.

Session 3D (Room 3, 3:30pm - 4:30pm)

· Speaker: Hani Dekaidek – Cadence - Principal Product Marketing Manager

· Title: AuraStack: Intent to Implementation in an Agentically Automated Workflow

· Abstract: The next generation of PCB design requires more than automation. It requires intelligent workflows that can understand design intent, coordinate engineering tasks, and optimize outcomes across the design process. Agentic AI is emerging as a new approach to addressing these challenges.

This presentation explores how agentic AI can assist PCB designers throughout the workflow, from schematic development and constraint creation to layout implementation and optimization. Using AuraStack™ as an example, attendees will learn how AI-driven orchestration and integrated analysis can help reduce manual effort, accelerate design iterations, and improve overall engineering productivity.

Session 4D (Room 4, 3:30pm - 4:30pm)

· Speaker: Alex Lin – ADLINK Technology – Senior Director

· Title: Palm-Sized Power: Designing and Manufacturing with OSM® and COM-HPC Mini

· Abstract: Edge-AI gateways and industrial controllers now need 32 GT/s PCIe, USB4, and TSN-ready Ethernet in spaces smaller than a credit card. Two open standards deliver that punch without overlapping:

• OSM® — solder-down LGA/BGA modules from 15 × 30 mm up to 45 × 45 mm, each carrying the SoC plus DDR memory and eMMC/SSD. One SMT reflow handles module + carrier, eliminating board-to-board connectors, memory compatibility debug, and half the real estate of a SMARC-L design.

• COM-HPC Mini — a 95 × 60 mm mezzanine card providing PCIe 5, USB4, and 25 GbE KR with scalable cooling for up to 45 W edge servers while preserving mid-life CPU swap flexibility.

The session distills both specs into PCB-level do’s & don’ts:

• Stack-up impedance rules for 20-inch PCIe 5/USB4 lanes

• LGA pad, stencil, and X-ray AOI guidelines for high-yield OSM reflow

• Connector breakout and keep-out tactics for COM-HPC Mini

• Thermal and power co-design—CFD tips and fan-less ΔT data

• DFM/DFT gates that lifted first-pass yield from 83 % → 95 %

• Decision tree for when to choose OSM vs. COM-HPC Mini and how to migrate between them

Session 5D (Room 5, 3:30pm - 4:30pm)

· Speaker: Oscar Sanchez – NXP – Product Line Director

· Title: Leading the Future of the Intelligent Edge: Scalable, Efficient, and Privacy Centric AI at the Device Level

Session 6D (Room 6, 3:30pm - 4:30pm)

· Speaker: Ryan Miller - NCAB Group (USA) - Field Application Engineer/Medical Tech Specialist

· Title: Advanced PCB Technologies

· Abstract: As electronic Medical Devices continue to shrink in size while increasing in performance, reliability, and functional density, the bare printed circuit board is no longer a passive commodity. It has become an "enabling technology" that directly influences electrical performance, manufacturability, and long-term product success. This presentation explores how rising product complexity across medical, industrial, aerospace, and high-performance computing markets is driving broader adoption of advanced interconnect architectures such as HDI and ultra HDI.

Attendees will gain insight into the key design and manufacturing pressures accelerating this shift, including fine pitch components, higher I O counts, signal integrity requirements, power integrity constraints, and aggressive form factor targets. The session will examine how technologies such as microvias, stacked and staggered via structures, sequential lamination, thinner dielectrics, and finer line width and spacing are being applied to meet these demands. Practical considerations around material selection, reliability tradeoffs, yield risk, and cost drivers will be discussed to help engineers understand when HDI or ultra HDI is justified and when it may introduce unnecessary complexity.

Through real world examples, this presentation will connect product level functional requirements to bare board fabrication strategy, highlighting how early collaboration between design teams and manufacturing partners can reduce risk and improve outcomes. The goal is to equip designers, engineering leaders, and program managers with a clearer framework for evaluating advanced PCB technologies and making informed decisions as product architecture continues to evolve.

Technical Sessions 2026 - Abstracts

This website uses cookies.