Technical Presentations 2025

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Room 2 - Keynote

• 8:22am From Automation to Autonomy: AI's Evolving Role in Printed Circuit Board Design
• Speaker:  Matt Bromley - Vice President Product Strategy and Technology, Siemens
• Abstract: The integration of artificial intelligence into printed circuit board (PCB) design offers significant potential to enhance productivity, address workforce shortages, and manage increasing design complexity. However, current AI technologies often lack the precision and repeatability required for critical engineering applications. While existing AI solutions face challenges in meeting rigorous validation requirements, emerging agentic AI systems present opportunities for cross-domain applications, including intelligent bridging of mechanical-electrical constraints, automated compliance verification, and multi-disciplinary design optimization. This keynote provides a balanced assessment of AI adoption in PCB design, advocating for strategic implementation that leverages current capabilities while preparing for next-generation autonomous design agents.

Presentation #1

• Title Switch-Mode Power Supply Layout – Best Practices for PCBA Design
• Speaker: Gerry Callahan - Senior Electrical Engineer, U.S. Cargo Systems
• Abstract:  Today's Switch-Mode Power Supply (SMPS) circuits are fast and efficient.  The speed is crucial to both size and efficiency, but that can make it difficult to pass agency tests such as FCC, while performing robustly in real-world conditions.  In this session, you will: see why SMPS presents specific challenges for EMI (Electro-Magnetic Interference); learn how not to compromise between minimum EMI and maximum efficiency (who really wants to sacrifice either one?); and discuss common problems and how to avoid them.  We will also see how this impacts agency testing (and how to pass the tests!), and discuss some recommended PCB stackups.  There is a live demonstration, audience discussion is encouraged, and there will be time for questions and answers.

Presentation #2

• Title Optimizing Engineering to Manufacturing Efficiencies
• Speaker: Stephen V. Chavez - Principal Technical Product Marketing Manager, Siemens
• Abstract:  Effective collaboration between designers and manufacturers is crucial for successful product development, particularly in the PCB industry. This abstract explores the critical relationship between design and manufacturing, emphasizing the importance of early-stage collaboration and Design for Manufacturing (DFM) implementation. This abstract highlights how PCB fabricators focus on transforming designs into physical boards that meet performance requirements, producibility standards, and economic constraints. 
• A key finding is that successful manufacturing outcomes depend on proactive DFM analysis throughout the design process, rather than reactive measures that can lead to costly iterations and delayed market entry. This abstract emphasizes the significance of comprehensive documentation, including detailed engineering drawings, manufacturing process instructions, and precise material specifications. Furthermore, the implementation of bi-directional feedback loops and early fabricator engagement has been shown to optimize the overall manufacturing process, leading to improved product quality and faster time to market.
• In summary, this abstract offers a comprehensive perspective where the industry best practice methodology bridges the gap between engineering and manufacturing requires a systematic approach that incorporates clear communication channels, standardized guidelines, and continuous optimization of the design-to-manufacturing handoff process, leading to a manufacturing driven design. This integrated approach not only enhances product quality and reduces defects but also promotes sustainable manufacturing practices and supply chain resilience.

Presentation #3

• Title Electromagnetics for the Working Engineer
• Speaker: Dr. Bruce Archambeault - IEEE Fellow, Missouri S&T Adjunct Professor 
• Abstract: Today’s electrical engineers must manage increasing responsibilities as designs become more complex and project timelines are reduced. Historically, to ensure reliable and compliant designs, signal integrity subject matter experts would need to validate that designs meet their specifications. This resulted in expensive bottlenecks, leading to delays in schedules, engineering change orders (ECOs), and a decrease in design quality. Allegro X System Capture introduced the EE Cockpit to bring more power to the EE during the design process by integrating design reliability and analysis capabilities. Electrical stress and mean time between failure (MTBF) analyses allow EEs to assess component and board reliability in different environmental conditions to help reduce field failures and increase product reliability. Additionally, the EE Cockpit shifts left signal and power integrity analysis so EEs can make critical engineering decisions early in the design phase to drive meaningful constraints to the layout designer.

Presentation #4

• Title Optimizing Scale-Up and Scale-Out Data Center and AI System Topologies with Samtec CPX Interconnect
• Speaker:  Matthew Burns - Global Director Technical Marketing, Samtec
• Abstract:  The combination of extreme-density, co-packaged interconnects, next-gen AI accelerators and 100 TB switches form the backbone of bleeding-edge AI and data center system topologies. Co-Packaged Copper (CPC) optimizes 224 Gbps signaling by eliminating BGA packaging losses. This implementation allows for extended reach preserving the viability of copper cable assemblies. Emerging Co-Packaged Optics (CPO) solutions enable high-bandwidth, low-latency optical links that can span multiple racks. 
• In this presentation, Samtec technical experts will detail next-gen CPC/CPO solutions using the same SMT Co-Packaged CPX connector. This new CPX architecture breaks through existing performance barriers allowing seamless interconnection in next gen switching topologies, scaling multiple GPUs, and enabling AI supercomputing fabrics. An overview of the latest 448 Gbps PAMx technologies will also be presented 

Presentation #5

• Title Don't Let Heat Derail Your Design: Thermal Considerations Upfront in PCB Design
• Speaker: Ryan Miller - FAE / Medical Tech Specialist, NCAB Group (USA)
• Abstract: Thermal management isn't an afterthought — it's a design strategy. Learn practical tips, simulation insights, and real examples that will help you design smarter, run cooler, and deliver faster.  Join us for an eye-opening session tailored for electrical engineers who are tired of scrambling to fix thermal issues late in the design process. Discover how early-stage thermal planning can:
•    • Improve reliability and performance
•    • Prevent costly redesigns
•    • Optimize component placement and PCB layout
•    • Align with real-world application conditions
• Printed Circuit Boards (PCBs) are often home to more than just copper traces—they can contain high-power, high-frequency, and active components that generate significant heat. Without proper thermal management, this excess heat can degrade performance or lead to complete system failure.
• This seminar will explore proven methods for managing heat in PCB design, starting at the layout stage. We’ll discuss how thermal simulations, strategic material selection, and modern manufacturing techniques can reduce thermal stress and maintain safe operating temperatures. From via farms to copper coins and insulated metal substrates, you’ll gain insight into the right heat dissipation techniques for different component needs.
• Design smarter, cooler, and more reliable PCBs—starting with thermal considerations up front.

Presentation #6

• Title FCT for RF/High Speed Applications with Test Probes. Strategies, Pitfalls and How to Avoid Those.
• Speaker: Matthias Zapatka - Senior Field Application Engineer, INGUN USA
• Abstract: In this presentation, we discuss how to successfully use test probes and test plugs to perform a functional test on printed-circuit board assemblies, with special focus on RF and High-Speed applications. What may work well for DC and general board test, may pose a big challenge for signals in the GHz range. Suddenly, conductors may have parasitic effects and may behave more like a capacitor or inductor. Overhanging pins may act like an antenna and signals may radiate from that part, which could cause havoc for unshielded components, especially applications where high sensitivity levels are required. Also, if parts are not impedance-matched, reflections can occur, which severely limits the usable frequency-range. But how to avoid all of that and how to optimize the DFT (design for test) strategy so that such signals can be successfully transmitted? Come and join us at PCB Carolina this November to find out. We also cover strategies to mitigate RFI/EMI, such as shielding. Armed with this knowledge, RF Design Engineers, Production Test Engineers, Board Design Engineers will get all knowledge they need to work on a test strategy for RF and High-Speed for the purpose of doing functional testing. Everything is covered from a technical perspective but described in a way that is very easy to follow for a broad audience with varying skill-level, from beginner to expert.

Presentation #7

• Title Inside the Module: State-of-the-Art Advances in Computer-on-Module Technology
• Speaker: Alex Lin - Senior Director of Product Sales Manager,  ADLINK
• Abstract: Computer-on-Module platforms have evolved from “processor mezzanines” into miniature HPC nodes that now rival 1U servers. This talk surveys the technical frontier, focusing on the new COM-HPC and next-gen COM Express pin-outs that enable:
• • I/O bandwidth: 400-pin connectors supporting 32 GT/s PCIe Gen 5 today and a clear path to Gen 6/7 in the same footprint. 
• • Compute density: 24-core hybrid Intel® architectures, integrated AI/VNNI engines, and up to 128 GB DDR5 on-module. 
• • High-speed networking: Native 10/25/100 GbE KR lanes and time-sensitive-networking (TSN) hooks for deterministic edge workloads. 
• • Scalability & serviceability: Module/carrier separation that lets OEMs refresh CPUs every few years while preserving costly compliance artifacts (EMC, safety, FDA, etc.).
• • Thermal & power design: Real-world data on cooling 65 W+ processors in fanless enclosures—heat-spreader options, vapor chambers, and SIM thermal simulation tips.
• Attendees will leave with a roadmap of which COM standards best fit next-generation edge-AI, defense, medical, and industrial automation designs—and what trade-offs to expect around signal integrity, PCB stack-up, and long-term availability. No product pitches—just practical engineering insight from 25 years of module evolution.

Presentation #8

• Title From Module to Market: A Practical Design-In Roadmap for Custom COM Carrier Boards
• Speaker: Ronny Tao - Senior Director of Product Sales Manager,  ADLINK
• Abstract: Picking a COM is only the first step—the real engineering begins when you marry that module to a purpose-built carrier. Drawing on two decades of hands-on design-in support, this session maps out a repeatable workflow that keeps projects on schedule and within budget:
• 1. Requirements capture: Translating functional specs into connector-pin budgets, power envelopes, and PCB layer counts.
• 2. Reference-design leverage: How to mine the PICMG COM-HPC Carrier Design Guide and proven schematics to shortcut risk. 
• 3. Signal-integrity & stack-up: Routing PCIe Gen 5, 25-GbE-KR, and USB4 while meeting ∆-T targets; choosing loss-optimized laminates.
• 4. Power-/Thermal-co-design: DC-DC stage selection, load-step validation, mechanical keep-out for heat spreaders, and CFD checkpoints.
• 5. Firmware & BSP hand-off: Secure boot, board-ID EEPROM, carrier-specific ACPI tables, and automated regression test hooks.
• 6. Design for X: Manufacturability, test, compliance, and—crucially for CMs—how to structure DFX reviews so issues surface before Gerber release.
• Real case studies illustrate pitfalls (e.g., marginal eye diagrams on 30-inch PCIe lanes) and the quick wins that shave weeks off EVT. Engineers, students, and contract manufacturers will gain a clear blueprint for turning any COM into a robust, certifiable product—whether the target is a handheld medical scanner or a ruggedized radar processor.

Presentation #9

• Title Understanding the CE Mark for Products Sold into the European Union
• Speaker: William (Bill) Bisenius - Director of Technical Services, Eurofins CertifiGroup
• Abstract: The European Union presents the 2nd largest market in the world, with nearly as much buying power as the United States. Which makes it a very attractive market for product manufacturers.
• •  But what does it take to import & sell your product in the European Union?
•     o It takes the CE Mark
• •  And how do you get the CE Mark?     
• This presentation will explain the European CE Mark requirements and give the attendee an understanding of what it takes to put the CE Mark on their product. No matter what type of product made/sold, there is a standardized process to follow in obtaining the CE Mark. This presentation will give you a solid understanding of the CE Mark requirements and cover each Directive in a manner that will apply to all product manufacturers and distributors, regardless of the type of product produced and sold. Attendees will leave the presentation with a confident feeling knowing that the CE Mark isn’t really the giant obstacle it appears to be and that they can sell their product in the EU! 

Presentation #10

• Title Next-Generation Techniques in Electronic Failure Analysis
• Speakers: Dr. Steven Crane - Director, Lab Services, ARA-I
• Abstract: Modern electronic design faces increasingly complex challenges as integration density and power demands rise. This presentation explores advanced techniques in failure mode and root cause analysis (FMRCA) that are valuable for diagnosing issues across a variety of common system designs, including power management, controls, and system protection, emphasizing practical methods for identifying and mitigating failures early in the design & manufacturing process. A key focus is the value of non-destructive techniques (NDTs) in detecting latent defects, accelerating root cause determination, and preserving evidence for corrective action.  Several case studies will highlight the value of utilizing a wide breadth of analytical techniques to improve diagnostic speed & accuracy, thereby reducing the cost of quality in critical electronic applications.

Presentation #11

• Title Dry Circuits, Wet World: How Parylene Coatings are Tested for Water Defense 
• Speaker: Alexander Niebroski - R&D Laboratory Manager, HZO Inc.
• Abstract: Parylenes are a type of polymer that have seen growing application in protecting PCBs from moisture, chemicals, and other harsh environmental factors. Chemical vapor deposition (CVD) performed under vacuum yields coatings with superior conformality and excellent chemical barrier, dielectric, and optical properties. To verify coating performance and consistency, a range of metrology techniques are employed, including water vapor transmission rate (WVTR), contact angle measurements, FTIR spectroscopy, nanoindentation, pencil hardness, and more. As demand for robust, high-performance electronics grows, ongoing innovation in both deposition and characterization technologies continues to expand the functional potential of Parylene coatings.

Presentation #12

• Title  Advanced Materials and Process for HDI Designs
• Speaker: Paul Cooke - Senior Director of Application Engineering, AGC
• Abstract: Designing printed circuit boards (PCB) and assemblies is more difficult than ever due to complexity, component availability, thermal requirements, signal integrity, material selection, layer counts, harsh environments and increased functionality all required in smaller form factors. We will look at all the elements to successfully manufacture a PCB that can meet all the designers’ requirements and perform to the customer and industry standards as well as survive in today’s harsh environments. We will look at some of the more advanced process’ and materials being adopted by the fabricators to produce smaller, thinner more reliable and faster production times to meet quick turn requirements. We will look at various processes and materials including plating shut, interposer designs, high reliability, high layer 5+ stacked microvia designs with 3 mil microvias, heavy copper solutions, and new hole fill processes without the need to planarize. All these processes need to ensure the product is robust as possible with a high level of confidence that it has been designed for extended life in the field.

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